Digital systems usually contain several individual elements. For example, a personal computer may have a central processing unit (CPU), a graphics processing chip, memory units, and other types of components. A central challenge in the design of digital systems is to provide reliable, error-free high speed communications between the various elements of a digital system.
High speed digital communications may be carried out by using either a parallel bus or a high speed serial bus. One example of a parallel bus is the Peripheral Component Interface (PCI) bus. The PCI bus is a parallel bus that is sixty four (64) bits wide and that is clocked at a speed of thirty three megahertz (33 MHz).
Large parallel bus systems such as the PCI bus have exhibited sufficient performance for existing personal computer systems. However, as the speed of digital communications systems increases, parallel bus structures are becoming widely recognized as having limitations. The limitations of parallel bus structures are due to the difference in propagation delay between the fastest line and the slowest line on a parallel bus.
High speed serial data links mitigate the problem presented by the propagation delay difference between the fastest line and the slowest line of a parallel bus by “embedding” a high speed clock signal within the data. The receiver receives the data with the embedded clock signal and extracts the clock information and the data simultaneously. The circuit that performs this function is referred to as a “clock and data recovery circuit” (CDR circuit).
A CDR circuit is connected to and interfaces with a data signal line that carries the incoming data stream. The CDR circuit performs the function of extracting the incoming data and clock information from the incoming data stream. This function is typically performed with an electronic control loop that detects the incoming data. Based on the data edge locations in time, the electronic control loop makes a determination of the instantaneous phase of the data.
The electronic control loop subsequently aligns the electronic control loop's own internal clock with the phase of the incoming data. This alignment allows the CDR circuit to sample the data in the middle of the bit period to ensure that a maximum signal-to-noise ratio is achieved. The aligned clock signal is also referred to as the recovered clock signal because it represents a clock signal that is synchronous with the recovered data.
There are two main architectures in the prior art that are used to construct a clock and data recovery (CDR) circuit. The primary difference between the two systems is the way the recovered clock signal is generated. A first CDR type system generates the recovered clock signal with a voltage controlled oscillator (VCO). The VCO based system is capable of generating the recovered clock signal at the same frequency as the data. In addition, the VCO based system can vary the recovered clock phase to match the phase of the data.
A second CDR type system uses a phase interpolator to vary the phase of a reference clock signal that is supplied to it from another on-chip block (typically, a phase-lock loop (PLL)) that produces a nominal clock frequency that matches the nominal frequency of the incoming data. The interpolator produces a new clock signal with an interpolated phase that is varied to match the phase of the incoming data. This clock signal is then used to sample the data in the middle of the bit period. The interpolated clock signal, in this case, is also referred to as a recovered clock signal. Even though this system (i.e., the interpolated phase system) uses a reference clock signal with a fixed frequency, it can still adjust the interpolated clock frequency to match the variation in frequency of the incoming data. The frequency shift is accomplished by continuously varying the phase of the interpolated clock signal to translate it into a frequency shift.
The electronic control loop uses a phase detector at its input to compare the phase of the incoming data to the phase of the internal clock signal. The phase detector determines whether the clock phase is early or late relative to the incoming data signal. The electronic control loop subsequently makes a decision to vary the phase of the internal clock signal in such a way as to eliminate the phase difference between the clock signal and the incoming data signal.
The data sampling is accomplished through the use of input comparators that are driven from one or more phases of the internal (i.e., recovered) clock signal. Under ideal conditions, these comparators sample each data bit in the middle of the bit period and make a determination whether the bit is zero or the bit is one and pass on the decision as the recovered data. A clock and data recovery (CDR) circuit of the phase interpolator variety tracks an incoming data stream by continuously varying the phase of the internal (i.e., recovered) clock signal through phase interpolation.
In order for a CDR circuit to accurately extract the embedded clock signal from the serial data stream, the CDR circuit may introduce only a small amount of clock jitter. Clock jitter may be created by several sources. For example, clock jitter may be due to residual error from the phase detection process. Clock jitter may also be due to local oscillator noise. Clock jitter may also be due to injected power supply noise.
Prior art serial link receivers often use a current mode logic (CML) style D flip flop circuit in the data sampling comparator circuit. CML D flip flop circuits have an advantage in that they use differential clocks and are therefore fairly immune to power supply noise because both the inverting and non-inverting clock inputs are essentially balanced during switching.
CML D flip flop circuits, however, have a disadvantage because the CML circuitry consumes static power. A second disadvantage of CML flip flop circuits is that their full differential output levels are not compatible with standard CMOS logic. It would be advantageous to provide a data sampling comparator of a clock and data recovery circuit that does not have these prior art disadvantages.
Therefore, there is a need in the art for a system and method for providing a clock and data recovery circuit that has comprises a low jitter data receiver. There is also a need in the art for a system and method for providing a clock and data recovery circuit that consumes less static power than the power consumed by CML D flip flop circuits. There is also a need in the art for a system and method for providing a clock and data recovery circuit that has a low transfer function of power supply noise to sampling clock jitter.